The present invention relates to a semiconductor memory device that uses MOS transistors as memory elements and is capable of writing and reading data.
A nonvolatile transistor used as a memory cell in an EEPROM, which erases data electrically, is generally composed of two layers of polycrystalline silicon separated by an insulating film as shown in FIG. 1. A floating gate 701 is made of a first polycrystalline silicon layer and a control gate 702 is made of a second polycrystalline silicon layer. Numeral 703 indicates a source, 704 a drain, 705 a silicon substrate, 706 a contact hole, and 707 a data line made of aluminum (Al). The data line passes through the contact hole 706 and is connected to the drain 704. The data write, read, and erase operations in a memory cell having the above structure will be described below.
Writing is done by setting the drain potential V.sub.D at 5.5 V, the control gate potential V.sub.CG at 10 V, and the source potential V.sub.S at 0 V and injecting hot electrons into the floating gate.
Erasing is done by setting the control gate potential V.sub.CG at -7 V, placing the drain potential V.sub.D in the floating state, and applying, for example, 6.5 V to the source. At this time, the electrons in the floating gate are pulled out by the tunnel effect.
Reading is done by setting the control potential V.sub.CG at 5 V, the drain potential V.sub.D at 0.8 V, and the source potential V.sub.S at 0 V. In this case, when "0" has been stored in the memory cell (in the written state), almost no current flows between the source and the drain. When the stored data is "1" (in the erased state), a cell current of about 60 .mu.A flows between the source and the drain.
In a nonvolatile semiconductor memory device using such transistors as memory cells, the distribution of the threshold voltages of the memory cell transistors after writing and erasing is very important.
The distribution of the threshold voltages of memory cells after erasure will be described using FIG. 2. In a memory cell, the threshold voltage generally varies in the range of about 2 to 3 V after erasure. The upper limit of variations in the threshold voltage is assumed to be Vthb. If the upper limit is lowered, the cell current in the memory cell as a whole will increase. This makes it possible to read the data from the memory cell at faster speeds.
When variations in the threshold voltage are great, the lower limit might be Vthc. If the lower limit is Vthc, the threshold voltage is lower than 0 V. Under this condition, when the data is read from a "0" cell on the same data line, leakage current will develop at a cell whose threshold voltage is lower than 0 V, which causes "1" to be read, resulting in a faulty operation. To prevent the faulty operation, it is necessary to set the threshold voltage after erasure at 0 V or higher (Vtha).
To examine variations in the threshold voltage in such a memory cell, a test circuit capable of externally monitoring the current in the memory cell is often provided.
FIG. 3 is a circuit diagram of the main section of a conventional semiconductor memory device equipped with a test circuit capable of externally monitoring the current in memory cells.
In the semiconductor memory device, a plurality of memory cells (not shown) arranged in a matrix within a memory cell array 21 are accessed by supplying signals to a row decoder 18 and column gates 20. The column gates 20 are controlled by a column decoder 19. The data items corresponding to the accessed memory cells are read in parallel via sense amplifier circuits (S/A0 to S/Ai) 22 and buffer circuits (Dout0 to Douti) 23. The read data items are outputted at pads IO0 to IOi. Namely, the memory cell array is divided into blocks. The data items corresponding to the accessed memory cells in each block are directed to specific pads.
Between the pads IO0 to IOi and data lines DL0 to DLi, transfer gates MT0 to MTi for use in an external monitoring are provided. When the monitor test signal "MONITOR" goes high, the cell current in the memory cell transistors of the memory cell array selected by the column decoder and row decoder via column gate transistors CT00 to CTij can be monitored externally at the pads IO0 to IOi.
In the structure of the test circuit, the transfer gates MT0 to MTi for monitoring are often provided near the memory cell array in order to suppress the generation of parasitic capacity on data lines DL0 to DLi. To carry the outputs of the gates to the pads, the gates need bus lines BUSCELL0 to BUSCELLi, respectively. Generally, the number of bits read in parallel is 8, 16, 32 or the like. Therefore, the number of bus lines results directly in an increase in the chip size of the memory device. That is, as the number of bits increases, the number of bus lines cannot be ignored accordingly.
To suppress an increase in the number of the bus lines, the output buses SAO0 to SAOi in the read circuit are sometimes forced to also act as BUSCELL0 to BUSCELLi. With such a structure, BUSCELL0 to BUSCELLi can be eliminated but an unwanted parasitic capacity is added to the output buses SAO0 to SAOi, leading to the degradation of the performance of the memory device.
The above-mentioned problems are summarized as follows.
In a conventional semiconductor memory device, a plurality of monitoring bus lines are required to equip the device with a test circuit for monitoring the current in each memory cell, which leads to an increase in the chip size. When another internal bus is caused to also serve as the monitoring bus, an unwanted parasitic capacity caused by the transfer gates for monitoring is added to the original internal bus, resulting in the degradation of the performance of the memory device.